Frequency Divider Circuit

 Frequency Divider Circuit

When the master clock is worked and everything is as expected. Then the next step is to build the frequency divider circuit. Since we don't have a lower crystal value the best way to get the low clock frequency value is to divide the master clock by using 2 counters and flip flop. The first counter will the divide the master clock by 32 and then feed into the D flip flop so that will give us 64kHz for bit clock. That 64kHz will divide by second counter by 8 will result 8kHz for FSYN. Since this circuit involved a lot of connection it is a good way to use a colour coding wire. Otherwise it can easily mess up the connection therefore create more problems. And also the chip must be probably grounded otherwise we are not getting the right frequency oscillating clock.